This invention relates to a memory device having valid bit storage units which are reset in batch.
Conventionally, in some of the memory devices, a valid bit storage unit was disposed at the head of the storage unit of data to be stored. That is, by placing a valid bit at the head of each word as the data to be stored, it is designed to indicate whether the subsequent word data is valid or invalid depending on whether that valid bit is 1 or 0. The memory device having such valid bit storage unit is used, for example, when simplifying the data control by hardware structure as disclosed in a constitution example of cache memory on page 138 of "Hardware of Microcomputer" of Iwanami Lecture on Microelectronics 5. Furthermore, on the same word as the data, a status bit storage unit for indicating the data control information may be provided.
In such conventional valid bit devices, however, if there are many unnecessary words in the stored word data depending on the changes in the status of the processing unit for executing the data, all data words were accessed, and the status bit storage unit and valid bit of each word were checked to judge unnecessary data words, and the valid bit of each word was rewritten to invalidate the unnecessary data.
In this method, if there are many unnecessary words, since accessing to the memory device and all words to be erased should be necessary, it becomes an extreme overload to the system including the memory circuit. Or, when erasing the words, it may be possible to set the data word line of all words at high potential and invalidate the valid bits, but in this case, necessary data may be erased together with unnecessary data.